In Universal Verification Methodology (UVM), managing the amount of simulation output is an important step in building a clean and readable verification environment. The concept of setting verbosity level in UVM allows engineers to control how much information is printed during simulation. This is useful for debugging, analyzing transactions, and understanding testbench behavior without being overwhelmed by unnecessary messages. Knowing how to set verbosity level properly helps improve productivity and ensures that the simulation log remains focused on the most important details.
Understanding UVM Verbosity
Verbosity in UVM refers to the level of detail in the messages generated by the verification components. The UVM report server handles these messages and filters them based on the current verbosity setting. This allows engineers to choose whether they want minimal information or detailed step-by-step outputs during simulation runs.
Why Verbosity Levels Matter
During the development of a testbench, there are times when engineers need very detailed information to troubleshoot issues. At other times, especially during regression runs, they only want to see errors and warnings to keep logs short. Setting verbosity level in UVM provides the flexibility to switch between these modes without rewriting code. This saves time and keeps the verification process efficient.
Common UVM Verbosity Levels
UVM provides several predefined verbosity levels. Each level determines which messages are displayed in the simulator console.
- UVM_NONENo messages except for errors and fatals are displayed. This keeps the log minimal.
- UVM_LOWDisplays basic information messages, useful for general simulation monitoring.
- UVM_MEDIUMPrints more detailed logs, including transactions and debug information.
- UVM_HIGHProvides verbose debugging output, useful for tracking detailed signal behavior.
- UVM_FULLPrints all available messages, including highly detailed internal processes.
How to Set Verbosity Level in UVM
Setting verbosity level in UVM can be done in multiple ways depending on whether you want to configure it globally or locally for specific components.
Global Verbosity Setting
A global verbosity level affects the entire testbench. You can set it in the testbench top file or in the simulation command line. For example
uvm_top.set_report_verbosity_level(UVM_MEDIUM);
This command ensures that all messages below the UVM_MEDIUM level are filtered out, giving you a balanced amount of information.
Component-Level Verbosity
If you want more control, you can set verbosity level for individual components. This is helpful when debugging a specific part of the design without flooding the log with messages from other components.
my_agent.set_report_verbosity_level(UVM_HIGH);
In this example, only the messages frommy_agentwill follow the UVM_HIGH verbosity level, while the rest of the testbench remains at the default level.
Using Command Line for Verbosity
Some simulators allow you to set verbosity level through command line options without modifying the source code. This is a convenient approach for running different levels of logging in regression scripts. For example
+UVM_VERBOSITY=UVM_HIGH
This approach allows flexibility and avoids recompilation of the testbench every time you want to change the verbosity setting.
Best Practices for Verbosity Management
Proper verbosity management ensures that the verification process is smooth and efficient. Here are some recommendations to follow when using verbosity levels in UVM
- UseUVM_NONEorUVM_LOWfor regression runs to keep logs short and focused.
- Switch toUVM_HIGHorUVM_FULLwhen debugging complex issues to get maximum detail.
- Apply verbosity selectively on components that are under investigation rather than the entire testbench.
- Combine verbosity settings with report server filters for even more precise control of output.
- Document the preferred verbosity levels for your team to maintain consistency across projects.
Debugging with Verbosity
When a test fails, increasing verbosity level can help engineers trace back the exact sequence of events leading to the failure. Detailed logging shows transaction data, sequence execution, and even internal UVM phases, making it easier to identify root causes.
Example Use Case
Suppose a test sequence fails because a monitor does not capture a transaction. By setting the monitor component verbosity to UVM_HIGH, you can see when and how transactions are being sampled, which can help locate timing or connection issues in the testbench.
Impact on Simulation Performance
It is important to note that higher verbosity levels may slow down simulation performance, especially when large logs are generated. Therefore, verbosity should be set carefully. Use high verbosity only when necessary and return to lower levels for normal regression runs.
Combining Verbosity with Severity Levels
UVM messages also have severity levels such asUVM_INFO,UVM_WARNING,UVM_ERROR, andUVM_FATAL. Verbosity levels filter messages based on their verbosity number, but severity filtering works independently. By combining both, you can choose to see only certain severities at a given verbosity level.
Learning how to set verbosity level in UVM is a crucial skill for anyone working with SystemVerilog-based verification environments. It gives engineers full control over the amount of information printed during simulation, making debugging faster and simulation logs cleaner. Whether using global verbosity settings, component-specific adjustments, or command line arguments, understanding how to manage verbosity helps create a more efficient verification flow. Balancing verbosity level appropriately ensures that you see the right amount of detail without overloading the log, leading to a more productive and streamlined verification process.